1. Field of the Invention
This invention relates to a semiconductor memory device and an electric device with the same.
2. Description of Related Art
Conventionally, various types of electrically rewritable and non-volatile semiconductor memory devices (EEPROMs) are known. Especially, a NAND-type EEPROM is known as one with a high integration level, in which plural memory cell are connected in series to constitute a NAND cell unit in such a manner that adjacent two memory cells share a source/drain layer. Usually, a MOS transistor, which has a charge storage layer (floating gate) and a control gate stacked on a semiconductor substrate, serves as a memory cell in the NAND-type EEPROM. This memory cell stores data in a non-volatile manner, which is defined by an amount of charge stored in the floating gate.
One end on a NAND cell unit is coupled to a bit line via a select gate transistor; and the other end to a source line via another select gate transistor. Control gates of the memory cells are coupled to different word lines, which are disposed as extending in a direction. A set of memory cells arranged along a word line constitutes a page (or two pages), which serves as a unit of data read and data write. A set of NAND cell units arranged along a word line (usually including 16 or 32 word lines) constitutes a block (or cell block), which serves as a unit of data erase. Usually, one cell array plane has plural blocks arranged in the bit line direction.
Disposed at one end of the bit lines is a sense amplifier circuit with a data latch, which serves as a page buffer; and disposed at one end of the word lines is a row decoder, which selects and drives a block and a word line. The cell array, page buffer and row decoder constitute a memory core. In a peripheral area of the memory core, there are disposed a high voltage generation circuit for generating various high voltages used for write, erase and read operations, a fuse circuit used for selecting redundant circuits, and a controller for controlling write and erase sequences and a read operation.
The cell array of the NAND-type EEPROM may be easily miniaturized because it is formed with a periodical pattern. However, it is required of transferring transistors, which are disposed in the row decoder to be coupled to word lines in the cell array, to be formed of high-voltage transistors (i.e., transistors subjected to a boosted voltage) with a channel length larger than that of the memory cells. By reason of this, it is impossible to dispose the transferring transistors at a word line pitch. To solve this problem, there have already been provided methods, in which the transferring transistors are dispersedly disposed at both ends of the word lines in the cell array (see, for example, JP7-230696A and JP2003-076880A).
In detail, the row decoder dispersing methods are classified into three types as follows: first, transferring transistors are disposed alternately on the right and left sides of the cell array for every word line; second, transferring transistors are disposed alternately on the right and left sides of the cell array for every block; third, transferring transistors are disposed alternately on the right and left sides of the cell array for every two blocks.
In the first scheme, give attention to a NAND cell unit disposed at end portion of a word line, further give attention to adjacent two word lines, and there is generated a difference between driving timings of two memory cells in the NAND cell unit controlled by the two word lines because driving ends of the two word lines are different. There is no driving timing problem in the second and third schemes because the driving ends of the entire word lines in a block are located on the same side.
Another problem of the dispersed transferring transistors is in the word line drawing wiring regions. It is required of word line drawing regions, which are defined for extending the word lines of the cell array to couple those to diffusion layers of the transferring transistors, to be changed in the line pitch for expanding the word line pitch. Therefore, the periodicity of line/space of the word lines is broken outside of the cell array, and this leads to difficulty of exposure. In consideration of this point, it is necessary for arranging the word line drawing portions. This causes the memory chip to be increased in area.